Peripheral devices that are compatible with the USB 2.0 standard typically have a serial interface engine block (SIE) and a parallel interface engine block (PIE). USB 2.0 peripheral devices employ SlEs and PIEs to transmit and receive data from host devices.
USB 2.0 peripherals, however, do not utilize the SIEs and PIEs at the same time. Instead, the SIEs are employed solely for peripheral operation in either the 1.5 Mbps low speed (LS) it operational mode or the 12 Mbps full-speed (FS) operational mode. Similarly, the PIEs are employed solely for peripheral operation in the 480 Mbps high speed (HS) operational mode. Therefore, during operation of a USB 2.0 peripheral, one interface engine block is active while the other interface engine block is inactive.
Despite the inactivity of one interface engine block, however, conventional USB 2.0 peripheral designs provide clock signals to both the SIE and the PIE regardless of the operational mode of the peripheral. Providing a clock signal to an inactive interface engine block results in USB 2.0 peripherals consuming more power than is necessary. Therefore, a need exists for a USB 2.0 peripheral that reduces power consumption by only providing a clock signal to the active interface engine block.